Module hazardflow_designs::cpu

RISC-V Sodor 5-stage.

References

• 5-stage constants: https://github.com/ucb-bar/riscv-sodor/tree/ef6d156fdafdcc79550ce12e45c7daf7a02a4e11/src/main/scala/sodor/rv32_5stage/consts.scala
• Memory op constants: https://github.com/ucb-bar/riscv-sodor/tree/ef6d156fdafdcc79550ce12e45c7daf7a02a4e11/src/main/scala/sodor/common/memory.scala#L28

Re-exports

• pub use alu::*;
• pub use branch_predictor::*;
• pub use csr::*;
• pub use decode::*;
• pub use exe::*;
• pub use fetch::*;
• pub use mem::*;
• pub use mem_interface::*;
• pub use multiplier::*;
• pub use riscv_isa::*;
• pub use wb::*;

Modules

• alu
  ALU.
• branch_predictor
  Related to branch prediction.
• csr
  CSR.
• decode
  Decode stage.
• exe
  Execute stage.
• fetch
  Fetch stage.
• mem
  Memory stage.
• mem_interface
  Memory.
• multiplier
  Multiplier.
• riscv32_5stage
  RISCV 5-stage pipeline CPU
• riscv_isa
  RISC-V Instruction. Currently supports
• wb
  Writeback stage.