Module hazardflow_designs::cpu::riscv_isa

RISC-V Instruction. Currently supports

• RV32I Base Instruction Set
• RV32/RV64 Zicsr Standard Extension
• Partial RISC-V Privileged Instruction Set including:
  • Trap-Return Instructions
  • Interrupt-Management Instructions

Structs

• BrInfo
  Branch information.
• Instruction
  Decoded instruction.

Enums

• BrType
  Branch type.
• Op1Sel
  ALU first operand data selector.
• Op2Sel
  ALU second operand data selector.
• WbSel
  Writeback selector.

Constants

• LEN_CSR_ADDR
  CSR Address is 12-bit.
• REGS
  Number of registers.

Functions

• imm_btype
  Extracts immediate for B-type instruction.
• imm_jtype
  Extracts immediate for J-type instruction.