Writeback stage

The writeback stage mainly do the following things:

  1. Write the result back to the destination register.

It can be decomposed into combinators as follows (code):

Input and Output

The IO interface type of the writeback stage is as follows:

Ingress

It takes an ingress interface with type I<VrH<MemEP, WbR>, { Dep::Demanding }>.

You can check the explanation of MemEP and WbR in here.

Egress

This is the last stage, it does not return any egress interface.

Behavior

Each combinator do the following things:

M0 (map_resolver_inner):

  • Constructs the ingress resolver of the writeback stage.
    • Attaches the bypassed data and register file for resolving data hazards.

M1 (reg_fwd):

  • Creates a pipelined stage before accessing regfile.
  • Sends a ready signal which indicates it will be free in the next cycle.

M2 (sink_fsm_map):

  • Updates the register file.
  • Attaches the register file to the resolver for reading value of source registers.