Memory stage

The memory stage mainly do the following things:

  1. Accesses memory for load/store instructions.
  2. Accesses CSR for illegal instruction and CSR instructions.

It can be decomposed into combinators as follows (code):

Input and Output

The IO interface type of the memory stage is as follows:

Ingress

It takes an ingress interface with type I<VrH<ExeEP, MemR>, { Dep::Demanding }>.

You can check the explanation of ExeEP and MemR in here.

Egress

It returns an egress interface with type I<VrH<MemEP, WbR>, { Dep::Demanding }>.

Each of MemEP and WbR is defined as a struct with the following fields:

MemEP (in mem.rs):

  • wb_info: Writeback information which contains the writeback address and data.
  • debug_pc: PC (for debugging purpose).
  • debug_inst: Instruction (for debugging purpose).

WbR (in wb.rs):

  • bypass_from_wb: Bypassed data from the writeback stage.
  • rf: Register file.

Behavior

Each combinator do the following things:

M0 (map_resolver_inner):

  • Constructs the ingress resolver of the memory stage.
    • Attaches the bypassed data and redirection PC for resolving data hazards.

M1 (reg_fwd):

  • Creates a pipelined stage before accessing DMEM or CSR.
  • Sends a ready signal which indicates it will be free in the next cycle.

M2 (map + branch):

  • Computes the branch selector with map combinator.
  • Branches the interface into three for accessing different module (DMEM / CSR / None).

M3 (map + comb):

  • Constructs DMEM request with map combinator.
  • Accesses the external DMEM module with comb combinator.
    • We use an asynchronous memory for memory, it provide the response in the same cycle.
    • We used attach_resolver and attach_payload to attach additional resolver/payload to the DMEM.

M4 (map_resolver_with_p + map):

  • Attaches the DMEM response to the resolver signal for the bypassing data calculation.
  • Constructs the memory stage egress payload with map combinator.

M5 (map + comb):

  • Constructs CSR request with map combinator.
  • Accesses the CSR module with comb combinator.
    • It provide the response in the same cycle.

M6 (map_resolver_with_p + map):

  • Attaches the CSR response to the resolver signal for the bypassing data calculation.
    • It contains the redirection PC when exception happens.
  • Constructs the memory stage egress payload with map combinator.

M7 (map_resolver_with_p + map):

  • Directly attaches the payload to the resolver signal bypassing data calculation.
  • Constructs the memory stage egress payload with map combinator.

M8 (merge):

  • Selects one of transferrable egress interface of M4 (DMEM), M6 (CSR), and M7 (None).
    • It is guaranteed to be processed in-order manner because the maximum concurrent instruction in the memory stage is limited to one.